Proprietary circuit layout identification

ABSTRACT

A method is provided for identifying use of a proprietary circuit layout. A representation of a layout of a circuit is input and the locations of a set of predetermined physical features of the circuit are identified. This set of locations is then compared with a previously generated characteristic pattern file, the characteristic pattern file comprising a representation of relative locations of a set of these predetermined physical features in the proprietary circuit layout. If the set of locations matches the relative locations of the characteristic pattern file, then an output is generated indicating that use of the proprietary circuit design has been found.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to proprietary circuit layouts. Moreparticularly, this invention relates to the identification of the use ofa proprietary circuit layout.

2. Description of the Prior Art

The owners of proprietary circuit layouts may wish to gather royaltypayments from those who choose to design, manufacture and/or usecircuitry incorporating such proprietary circuit layouts. However,whilst most manufacturers and end users will make royalty payments tothe owner fairly corresponding to their usage of these proprietarycircuit layouts, the complexity of modem circuit designs may mean thatsome royalties are not gathered, due to the difficulties of tracking theusage of particular proprietary circuit layouts.

For this reason, in order to seek to identify usage of their proprietarycircuit layouts, it is known for proprietary circuit layout owners toadd information to their circuit layouts which will enable them later toreadily identify a given circuit as containing one or more of theirproprietary circuit layouts. For example, a circuit designer who issuescircuit layouts in the form of an IP library may embed tagging datawithin the circuit layouts held in that IP library, relying ontechniques for identifying that embedded tagging data at a later stagein the circuit production process to identify usage of their proprietarycircuit layouts. Such a technique is described in the document “VirtualComponent Identification Physical Tagging Standard 1.3.0 (retrievablefrom http://www.vsi.org/docs/IPP_Tagging_Std%201_(—)30.pdf). However, asignificant drawback of this technique is that the end user, the foundryor integrated device manufacturer (IDM) can inadvertently remove thistagging data, or even intentionally remove it, such that identificationof the proprietary circuit layout by this method is not possiblethereafter.

An alternative technique for embedding tagging information is“watermarking” such as that described in “VLSI Implementation of OnlineDigital Watermarking Technique with Difference Encoding for 8-Bit GrayScale Images”, Garimella et al., VLSID pp. 283, 16^(th) InternationalConference on VLSI Design, 2003-1063-9667/03 IEEE. This describes amethod of adding information to proprietary digital content to identifythe owner of that digital content.

All such prior art techniques suffer from the same fundamentaldisadvantage, that tagging data or watermarks must not only be added inthe first place, but can still be removed either accidentally orintentionally, and the circuit designer then loses the ability to trackuse of his proprietary circuit layouts for royalty purposes.

Hence, it would be desirable to provide an improved technique foridentifying use of proprietary circuit layouts.

SUMMARY OF THE INVENTION

Viewed from a first aspect, the present invention provides a method ofgenerating a characteristic pattern file to be used to identify use of aproprietary circuit layout, the method comprising the steps of:inputting a layout database file comprising a representation of saidproprietary circuit layout; extracting relative locations of a set ofpredetermined physical features of said proprietary circuit layout fromsaid layout database file; and generating said characteristic patternfile comprising a representation of said relative locations of said setof predetermined physical features of said proprietary circuit layout.

The inventors of the present invention realised that identification ofthe use of a proprietary circuit layout could be carried out, withoutthe need to embed or append additional information to that proprietarycircuit layout. In particular they realised that a proprietary circuitlayout could be identified with a high level of certainty, by referenceto the relative locations of a set of predetermined physical features ofthe proprietary circuit layout.

Furthermore, the inventors realised that it is possible to identify therelative locations of this set of predetermined physical features from alayout database file (for example an ‘IP library’) comprising arepresentation of the proprietary circuit layout. Here the term“relative locations” should be understood to encompass absolutelocations (e.g. a set of defined coordinates in a specified coordinatesystem) as well as a set of coordinates that are only defined relativeto one another. By doing this a characteristic pattern file comprising arepresentation of these relative locations can be generated, for use inlater identifying use of that proprietary circuit layout.

In other words, the techniques of the present invention seek to identifya proprietary circuit layout based on physical, non-removable,characteristics of the circuit, rather than on watermarks or taggingthat could be removed. Two advantages of this approach are that on theone hand no modification of the circuit layout is required (e.g. notagging data needs adding), whilst on the other hand identification ofthe proprietary circuit layout relies on physical characteristics of thecircuit itself, which thus could not be removed by an end user withoutcompromising the function of the circuit. The techniques of the presentinvention have the further advantage that they are “backwardscompatible” to circuits produced even before these techniques were firstput into practice, since the identification relies on inherentcomponents of the circuit and not on particular added tags orwatermarks.

It will be recognised that there are a number of ways that the relativelocations could be extracted. In one embodiment the extracting stepcomprises: parsing said layout database file to identify elementsindicative of said set of predetermined physical features; anddetermining said relative locations of said set of predeterminedphysical features from said elements. The layout database file may wellcomprise a considerable amount of information beyond that necessary toidentify these predetermined physical features, so it is advantageous tofirst parse the layout database file to identify elements which areindicative of the set of predetermined physical features, and then todetermine the relative locations of the set of predetermined physicalfeatures from those elements.

The elements selected to permit identification of the predeterminedphysical features could take a variety of forms, but in one embodimentthe identification is performed on a geometrical basis and the elementscomprise geometric shapes representing the predetermined physicalfeatures.

It may be the case that a given type of predetermined physical featureswill provide a sufficiently numerous set for the identification purposesof the present invention. However in one embodiment, if a count of afirst type of predetermined physical features is less than apredetermined lower limit defined by an extraction rule, at least asecond type of predetermined physical features is included in said setof predetermined physical features. Thus, by the inclusion of at leastone further type of predetermined physical features the population ofthe set is increased, such that subsequent identification using this setis then more reliable.

Whilst the layout database file could only contain a representation of asingle proprietary circuit layout, in one embodiment the layout databasefile is a library of proprietary circuit layouts and thus the layoutdatabase file comprises representations of a plurality of proprietarycircuit layouts.

When the layout database file comprises multiple proprietary circuitlayouts in this manner, it can be advantageous to select a particularproprietary circuit layout from which to extract the relative locationsof the set of predetermined physical features and in one embodiment theextracting step comprises selecting said proprietary circuit layout fromamongst said plurality of proprietary circuit layouts in dependence onan extraction rule.

It will be recognised that various extraction rules could be defined inthis context, but in one advantageous embodiment the extraction rulecomprises a constraint on a count of said predetermined physicalfeatures in said proprietary circuit layout. It has been found that ifthe count of the predetermined physical features in a given proprietarycircuit layout is too low, then the resulting relative locations thatare extracted would risk too many false positive identifications of useof the proprietary circuit layout. On the other hand, it has been foundthat if the count of the predetermined physical features in a givenproprietary circuit layout is too high, then the computational resourcerequired to perform use identification on this basis is unattractivelyhigh. An extraction rule constraining this count to fall within thesetwo limits is advantageous.

In one embodiment the parsing step is performed with reference toadditional information, the additional information comprising at leastone of: product information; foundry information; process information;and layer information. This additional information allows the parsing tobe carried out in a more targeted fashion, for example with respect to agiven layer of the proprietary circuit layout. Whilst the additionalinformation could be derived from a number of sources, in one embodimentthe additional information is contained within tapeout information.

The set of predetermined physical features could be arranged in avariety of ways in the proprietary circuit layout, but in one embodimentthe set of predetermined physical features is disposed in apredetermined layer of said proprietary circuit layout. Thisadvantageously simplifies the identification process.

In one embodiment the extracting step is performed with reference to apredetermined set of extraction rules. These extraction rules may forexample govern the manner in which the extraction is carried out, theformat of the relative locations extracted, the nature of the set ofpredetermined physical features, and so on.

Whilst all of the examples of a predetermined physical feature that areidentified in a proprietary circuit layout could be used, in oneembodiment the extracting step comprises selecting a subset of saidpredetermined physical features as said set of predetermined physicalfeatures.

It will be recognised that the layout database file could have manydifferent formats. In one embodiment the layout database file comprisesat least one GDSII (Graphical Data System II format) file. In anotherembodiment the layout database file comprises at least one of an OASIS(Open Artwork System Interchange Standard format) file; a GERBER file;and a DXF file.

Whilst various different varieties of physical feature could inprinciple be used, it has been found to be advantageous when said set ofpredetermined physical features comprises a set of contacts of saidproprietary circuit layout. In particular it is advantageous when thesecontacts are metal-poly contacts. Such features present a set which arereadily identified when generating the characteristic pattern file andwhich typically occur in numbers suitable for the present identificationpurposes. However, if a second type of predetermined physical featuresis required in order to supplement the numbers of the set, in oneembodiment the first type of predetermined physical features comprisesmetal-poly contacts and the second type of predetermined physicalfeatures comprises diffusion contacts.

Other example physical features can be used. In another embodiment theset of predetermined physical features comprises features of saidproprietary circuit layout selected from: features in a diffusion layer;features in a metal layer; vias; and transistor locations and/or sizes.

For the purposes of simplifying the generation of the characteristicpattern file and its later comparison to a circuit under investigation,in one embodiment the relative locations of said set of predeterminedphysical features of said proprietary circuit layout are defined byrelative origins of said set of predetermined physical features.

The set of predetermined physical features could in principle be anyphysical features of the proprietary circuit layout, but in oneembodiment the set of predetermined physical features comprisescircuitry components of said proprietary circuit layout. This results ina particularly durable identification method, since circuitry componentsare by their nature inherent to the function of the proprietary circuitlayout and thus their removal is likely to compromise that function.

Viewed from a second aspect, the present invention provides a method ofidentifying use of a proprietary circuit layout, the method comprisingthe steps of: inputting a representation of a layout of a circuit;identifying locations of a test set of predetermined physical featuresof said circuit from said representation; comparing said locations witha previously generated characteristic pattern file, said characteristicpattern file comprising a representation of relative locations of acharacteristic set of predetermined physical features in saidproprietary circuit layout; and generating an output indicative of aresult of said comparing step.

Further to the discussion of the first aspect of the present invention,in a related fashion the second aspect of the present invention allowsidentification of the use of a proprietary circuit layout to be carriedout, without the need to refer to previously embedded or appendedadditional information. Usage of a proprietary circuit layout can thusbe identified with a high level of certainty, and without a burdensomenumber of false positive identifications, by comparison to a previouslygenerated characteristic pattern file comprising a representation of therelative locations of a set of predetermined physical features of theproprietary circuit layout.

It will be recognised that there are a number of ways that the step ofidentifying locations could be performed. In one embodiment theidentifying step comprises: parsing said representation to identifyelements indicative of said test set of predetermined physical features;and determining said locations of said test set of predeterminedphysical features from said elements. The representation may wellcomprise a considerable amount of information beyond that necessary toidentify these predetermined physical features, so it is advantageous tofirst parse the representation to identify elements which are indicativeof the test set of predetermined physical features, and then todetermine the locations of the test set of predetermined physicalfeatures from those elements.

The elements selected to permit identification of the predeterminedphysical features could take a variety of forms, but in one embodimentthe identification is performed on a geometrical basis and the elementscomprise geometric shapes representing said test set of predeterminedphysical features.

It may be the case that the locations of the test set of predeterminedphysical features of the circuit may cover a larger area than therelative locations represented in the characteristic pattern file and inone embodiment the comparing step comprises panning across saidlocations of said test set of predetermined physical features to seek amatch with said characteristic set of predetermined physical features.

In one embodiment the parsing step is performed with reference toadditional information comprised in said representation, said additionalinformation comprising at least one of: product information; foundryinformation; process information; and layer information. This additionalinformation allows the parsing to be carried out in a more targetedfashion, for example with respect to a given layer of the circuit.Indeed in one embodiment the set of predetermined physical features isdisposed in a predetermined layer of said circuit.

It will be recognised that the representation could have many differentformats. In one embodiment the representation of said layout of saidcircuit comprises a GDSII tapeout. In another embodiment therepresentation of said layout of said circuit comprises at least one of:an OASIS file; a GERBER file; and a DXF file.

Whilst various different varieties of physical feature could inprinciple be used, it has been found to be advantageous when said testset of predetermined physical features comprises a set of contacts ofsaid circuit. In particular it is advantageous when these contacts aremetal-poly contacts. Such features present a set which are readilyidentified in the representation of the layout of the circuit.

Other example physical features can be used. In another embodiment thetest set of predetermined physical features comprises features of saidcircuit selected from: features in a diffusion layer; features in ametal layer; vias; and transistor locations and/or sizes.

For the purposes of simplifying the comparison of the locations with thepreviously generated characteristic pattern file, in one embodiment thelocations of said test set of predetermined physical features of saidcircuit are defined by relative origins of said set of predeterminedphysical features.

The test set of predetermined physical features could in principle beany physical features of the circuit, but in one embodiment the test setof predetermined physical features comprises circuitry components ofsaid circuit. This results in a particularly durable identificationmethod, since circuitry components are by their nature inherent to thefunction of the circuit and thus their removal is likely to compromisethat function.

Viewed from a third aspect, the present invention provides a dataprocessing apparatus for generating a characteristic pattern file to beused to identify use of a proprietary circuit layout, the dataprocessing apparatus comprising: input circuitry configured to input alayout database file comprising a representation of said proprietarycircuit layout; extraction circuitry configured to extract relativelocations of a set of predetermined physical features of saidproprietary circuit layout from said layout database file; andgeneration circuitry configured to generate said characteristic patternfile comprising a representation of said relative locations of said setof predetermined physical features of said proprietary circuit layout.

Viewed from a fourth aspect, the present invention provides a dataprocessing apparatus for generating a characteristic pattern file to beused to identify use of a proprietary circuit layout, the dataprocessing apparatus comprising: input means for inputting a layoutdatabase file comprising a representation of said proprietary circuitlayout; extraction means for extracting relative locations of a set ofpredetermined physical features of said proprietary circuit layout fromsaid layout database file; and generation means for generating saidcharacteristic pattern file comprising a representation of said relativelocations of said set of predetermined physical features of saidproprietary circuit layout.

Viewed from a fifth aspect, the present invention provides acomputer-readable storage medium storing a computer program which whenexecuted causes a computer to carry out the method according to thefirst aspect.

Viewed from a sixth aspect, the present invention provides a dataprocessing apparatus for identifying use of a proprietary circuitlayout, the data processing apparatus comprising: input circuitryconfigured to input a representation of a layout of a circuit;identification circuitry configured to identify locations of a test setof predetermined physical features of said circuit from saidrepresentation; comparison circuitry configured to compare saidlocations with a previously generated characteristic pattern file, saidcharacteristic pattern file comprising a representation of relativelocations of a characteristic set of predetermined physical features insaid proprietary circuit layout; and generation circuitry configured togenerate an output indicative of a result of said comparing step.

Viewed from a seventh aspect, the present invention provides a dataprocessing apparatus for identifying use of a proprietary circuitlayout, the data processing apparatus comprising: input means forinputting a representation of a layout of a circuit; identificationmeans for identifying locations of a test set of predetermined physicalfeatures of said circuit from said representation; comparison means forcomparing said locations with a previously generated characteristicpattern file, said characteristic pattern file comprising arepresentation of relative locations of a characteristic set ofpredetermined physical features in said proprietary circuit layout; andgeneration means for generating an output indicative of a result of saidcomparing step.

Viewed from an eighth aspect, the present invention provides acomputer-readable storage medium storing a computer program which whenexecuted causes a computer to carry out the method of the second aspect.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will be described further, by way of example only,with reference to embodiments thereof as illustrated in the accompanyingdrawings, in which:

FIG. 1 schematically represents a proprietary circuit layout and theextracted relative locations of a set of predetermined physical featuresof that proprietary circuit layout;

FIG. 2 schematically represents a series of modules for extractingrelative locations of a set of predetermined physical features andgenerating a characteristic pattern file;

FIG. 3 schematically represents a series of modules for identifyinglocations of a test set of predetermined physical features of a circuitand comparing those locations with a characteristic pattern file;

FIG. 4 is a flow diagram illustrating a series of steps performed whencomparing a test set of predetermined physical features of a circuitwith a characteristic pattern file; and

FIG. 5 schematically represents a general purpose computer suitable forcarrying out the techniques of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 1 schematically illustrates a plan view of a proprietary circuitlayout generally indicated 10. This proprietary circuit layout 10 iscomposed of different components typically arranged over several layers.These components include metal layer features, poly layer features,metal-poly contacts, diffusion contacts, diffusion layer features andvias. Also illustrated in FIG. 1 and generally indicated as 20 are a setof points indicating the relative locations of the metal-poly contactsin proprietary circuit layout 10. In other words, the collection ofpoints 20 illustrates the proprietary circuit layout 10 when allcomponents other than the metal-poly contacts have been removed. The setof metal-poly contact locations 20 thus represents a pattern which ischaracteristic of the proprietary circuit layout, and may be used toidentify the use of proprietary circuit layout 10 in a circuit undermanufacture as is described hereinafter.

FIG. 2 schematically illustrates the process of extracting relativelocations of a set of predetermined physical features and generating acharacteristic pattern file. The process begins with IP library 100,which contains representations of the layout of a number of proprietarycircuit layouts. In general the IP library may comprise memory, standardcell and IO libraries. In this example, the IP library database ishierarchically arranged in GDSII format, providing a memory efficientstorage format. Proprietary circuit layouts that are reused many times(e.g. a flip-flop layout) exist as ‘leaf cells’ at the lowest level ofthe hierarchy.

The IP library 100 forms the stream input for characteristic patternfile generator 110, which is embodied in a general purpose computer. Thecharacteristic pattern file generator comprises stream parser 120,pattern extractor 130 and storage engine 140. Thus it can be seen thatin this embodiment modules 120, 130 and 140 are provided as softwaremodules, although in another embodiment these modules may be provided ashardware units. Stream parser 120 reformats the stream input into aformat suitable for pattern extraction and passes this reformatted datato pattern extractor 130. In this example embodiment, in order to limitmemory usage the stream parser parses one leaf cell from the IP library100 at a time.

The stream parser 120 also operates with reference to tapeoutinformation 150 which represents additional information comprisingproduct information, foundry information, process information and layerinformation. For example, a leaf cell corresponding to a proprietarycircuit layout of a flip-flop is processed by stream parser 120 withreference to the particular layer in which the metal-poly contacts ofthat flip-flop are arranged. Pattern extractor 130 then identifies themetal-poly contacts from their geometrical representation in that layer(e.g. a set of rectangular features) and generates a characteristicpattern file comprising a representation of the relative locations ofthis set of metal-poly contacts. These relative locations are generatedin this embodiment as the origins (geometrical centres) of eachgeometrical object. Using the origin of the predetermined physicalfeatures has the advantage that adjustments to the size and shape ofthose features (for example as part of Design For Manufacturability(DFM) or Optical Proximity Correction (OPC) adjustments) will typicallynot significantly affect the relative origins of those features.Although this embodiment focuses on the relative locations of the set ofmetal-poly contacts, in other embodiments alternatively (or in addition)the features may be taken from another layer, for example a diffusionlayer or a metal layer. Alternatively (or in addition)through-connections between layers such as vias may be used.

The pattern extractor 130 acts with reference to extraction rules 160,which determine how the pattern extraction should be carried out. Anexample extraction rule is a constraint on the number of metal-polycontacts which the pattern extractor translates into the characteristicpattern file. If for example the number of metal-poly contacts exceeds apredetermined limit, the pattern extractor may choose to ignore somemetal-poly contacts according to predetermined rules, or alternativelythis particular proprietary circuit layout may be rejected as beingunsuitable for generating a characteristic pattern file. Thus theextraction rules can be used to select particular proprietary circuitlayouts from the IP library that are deemed particularly suitable forlater identification, for example due to the number of metal-polycontacts that they have.

Another example extraction rule causes the pattern extractor toadditionally extract the diffusion contacts if the number of metal-polycontacts does not reach a predetermined lower limit. By additionallyincluding the diffusion contacts, the total number of contacts extracted(i.e. the number of elements in the set of predetermined physicalfeatures) can be increased such that the characteristic pattern filegenerated is more reliable for identification of use of this particularproprietary circuit layout.

The generated characteristic pattern file (also known as a ‘goldenpattern’) is passed to storage engine 140 which stores thatcharacteristic pattern file in golden pattern database 170. Typically,the extraction process is performed iteratively on the IP library,parsing one leaf cell at a time and extracting a characteristic patternif one exists that meets the extraction rules 160.

FIG. 3 schematically illustrates the process by which the use of aproprietary circuit layout is identified. This process will typicallytake place at a foundry or integrated device manufacturer (IDM) where anintegrated circuit is being produced from a tapeout. Here, a tapeout (inthis example in GDSII format) represents the circuit being manufactured.This GDSII tapeout forms the input to pattern comparer 210, which isembodied by a general purpose computer. Pattern comparer 210 comprisesstream parser 220, test pattern extractor 230 and scanner 240. Thus itcan be seen that in this embodiment modules 220, 230 and 240 areprovided as software modules, although in another embodiment thesemodules may be provided as hardware units. Stream parser 220 inputs theGDSII tapeout and converts it into a format from which a test patterncan be extracted by test pattern extractor 230. The stream parser 220thus operates in a similar fashion to stream parser 120 and also makesuse of additional information in the tapeout comprising productinformation, foundry information, process information and layerinformation. For example, stream parser 220 may only parse informationrelating to a particular layer in which metal-poly contacts are expectedto be arranged.

In this example the test pattern extractor 230 operates in a similarfashion to pattern extractor 130 in FIG. 2, in that it identifiescontacts in a particular layer of the circuit and extracts theirlocations. Here, all contacts are extracted, including both themetal-poly contacts and the diffusion contacts. In particular, testpattern extractor 230 extracts the relative origins of the contacts.This set of locations is then passed to scanner 240 which compares thistest pattern with each target golden pattern stored in golden patterndatabase 170 (FIG. 2). Having done so, scanner 240 generates a patternmatching report 250 indicative of whether any of the target goldenpatterns have been found in the test patterns extracted.

The operation of scanner 240 is now described with reference to the flowdiagram illustrated in FIG. 4. The flow begins at step 300 and at step310 an extracted test pattern is inputted into scanner 240. At step 320the variable T is set to zero and at step 330 target pattern T isretrieved from the golden pattern database 170. At step 340 the variablei is set to zero and at step 350 the first point of the target patternis aligned with the first extracted test pattern point. Then, at step360, it is checked whether there is a match for the i^(th) point of thetarget pattern. Since the first (0^(th)) point of the target pattern hasbeen aligned at step 350 with a point in the test pattern, for thisfirst iteration a match will always been found. At step 370 the variablei is incremented by one. At step 380 it is checked if i now exceedsi_(max) (i_(max) being the total number of points in the current targetpattern). If i does not exceed i_(max) then the flow returns to step 360and a iterative process continues checking for a match for the i^(th)point, i.e. cycling through each point of the target pattern to see ifit matches with a point in the extracted test pattern. It should benoted that a positive match between a point of the target pattern andthe extracted test pattern (step 360) results from the locations of thetwo points coinciding within a predetermined tolerance. This toleranceis selected by the system administrator such that it is neither toostrict (resulting too many false negatives) nor too relaxed (resultingin too many false positives). In this embodiment, the predeterminedtolerance is set such that no false positive identifications occur, andsuch that overall a 6σ confidence level of identification of a givenproprietary circuit layout in a circuit under test can be achieved.

If at any stage there is not a match the flow exits the iterative loopand proceeds to step 390, where the target pattern is panned on the testpattern to try to match a pair of points, i.e. it is attempted to alignthe first point of the target pattern with a new point in the testpattern. This panning is necessary if the extracted test pattern coversa larger area than the target pattern. Panning may in particular benecessary if the tapeout has been ‘flattened’, i.e. the hierarchicalmemory-saving structure has, at least partially, been abandoned, suchthat a given instance of a circuit layout is represented multiple timesin the tapeout (rather than occurring in a single instance that isreferences multiple times). In a more simple scenario there may be noneed to pan the target pattern and steps 390 and 400 may effectively beignored, passing straight to step 410.

If such alignment (i.e. pairing) is possible by panning, then from step400 the flow returns to step 340, where the variable i is reset to zero.The new first point pair are aligned with one another at step 350 andthe iterative matching process of steps 360, 370 and 380 continues. Ifhowever a new pair of contacts is not possible, at step 400 the flowproceeds to step 410 where the variable T is incremented by 1. At step420 it is tested whether T now exceeds T_(max) (i.e. the total number oftarget patterns in the golden pattern database). If T does exceedT_(max), then at step 430 the scanner 240 generates a pattern matchingreport 250 indicating that no matching target patterns have been found.At step 440, if more test patterns need to be scanned, the flow returnsto step 310 to input the next extracted test pattern. If on the otherhand all test patterns have been scanned then the flow concludes at step450.

Returning to step 380, if i does exceeds i_(max), then the flow proceedsto step 460 where scanner 240 generates a pattern matching report 250indicating that a matching target pattern has been found. At step 465 Tis incremented by one and at step 470 it is tested whether T now exceedsT_(max) (i.e. the total number of target patterns in the golden patterndatabase). If it does, then at step 480, it is checked if more testpatterns need to be scanned. If there are more test patterns to scan,the flow returns to step 310 to input the next extracted test pattern.If on the other hand all test patterns have been scanned the flowconcludes at step 450. If at step 470 it is established that T does notexceed T_(max), then the flow proceeds via step 490 where it isdetermined whether scanning should continue, i.e. whether this extractedtest pattern should continue to be tested against other target patternsin the database, despite having already being found to match with one ofthose target patterns. If scanning should continue, the flow proceeds tostep 330. If scanning should not continue, then the flow returns to step310 and a new extracted test pattern is inputted for scanning.

FIG. 5 schematically illustrates a general purpose computer 500 of thetype that maybe used to implement the above described techniques and inparticular the characteristic pattern file generator 110 in FIG. 2 andthe pattern comparer 210 in FIG. 3. The general purpose computer 500includes a central processing unit 502, a random access memory 504, aread only memory 506, a network interface card 508, a hard disc drive510, a display driver 512 and monitor 514 and a user input outputcircuit 516 with a keyboard 518 and mouse 520, all connected via acommon bus 522. In operation the central processing unit 502 willexecute computer program instructions that may be stored in one or moreof the random access memory 504, the read only memory 506 and the harddisc drive 510, or dynamically downloaded via the network interface card508. The results of the processing performed may be displayed to a uservia the display driver 512 and a monitor 514. User input for controllingthe operation of the general purpose computer 500 may be received viathe user input output circuit 516 from the keyboard 518 or mouse 520. Itwill be appreciated that the computer program can be written in avariety of different computer languages. A computer program may bestored and distributed on a recording medium or dynamically downloadedto the general purpose computer 500. When operating under control of anappropriate computer program, the general purpose computer 500 canperform the above described techniques and can be considered to form anapparatus for performing the above described techniques. In particularthe general purpose computer 500 can perform the tasks of both thecharacteristic pattern file generator 110 in FIG. 2 and the patterncomparer 210 in FIG. 3. The architecture of the general purpose computer500 could vary considerable and FIG. 5 is only one example.

In summary therefore, according to the techniques of the presentinvention, a method, apparatus and program are provided for identifyinguse of a proprietary circuit layout. A representation of a layout of acircuit is inputted and the locations of a set of predetermined physicalfeatures of the circuit are identified. This set of locations is thencompared with a previously generated characteristic pattern file, thecharacteristic pattern file comprising a representation of relativelocations of a set of predetermined physical features in the proprietarycircuit layout. If the set of locations matches the relative locationsof the characteristic pattern file, then an output is generatedindicating that use of the proprietary circuit layout has been found.

Use of a proprietary circuit layout can thus be determined, only byreference to physical features of the circuit and without the need torefer to additional tagging or watermarking information.

Although particular embodiments of the invention have been describedherein, it will be apparent that the invention is not limited thereto,and that many modifications and additions may be made within the scopeof the invention. For example, various combinations of the features ofthe following dependent could be made with the features of theindependent claims without departing from the scope of the presentinvention.

1. A method of generating a characteristic pattern file to be used toidentify use of a proprietary circuit layout, the method comprising thesteps of: inputting a layout database file comprising a representationof said proprietary circuit layout; extracting relative locations of aset of predetermined physical features of said proprietary circuitlayout from said layout database file; and generating saidcharacteristic pattern file comprising a representation of said relativelocations of said set of predetermined physical features of saidproprietary circuit layout.
 2. The method as claimed in claim 1, whereinsaid extracting step comprises: parsing said layout database file toidentify elements indicative of said set of predetermined physicalfeatures; and determining said relative locations of said set ofpredetermined physical features from said elements.
 3. The method asclaimed in claim 2, wherein said elements comprise geometric shapesrepresenting said predetermined physical features.
 4. The method asclaimed in claim 1, wherein if a count of a first type of predeterminedphysical features is less than a predetermined lower limit defined by anextraction rule, at least a second type of predetermined physicalfeatures is included in said set of predetermined physical features. 5.The method as claimed in claim 1, wherein said layout database filecomprises representations of layouts of a plurality of proprietarycircuit layouts.
 6. The method as claimed in claim 5, wherein saidextracting step comprises selecting said proprietary circuit layout fromamongst said plurality of proprietary circuit layouts in dependence onan extraction rule.
 7. The method as claimed in claim 6, wherein saidextraction rule comprises a constraint on a count of said predeterminedphysical features in said proprietary circuit layout.
 8. The method asclaimed in claim 2, wherein said parsing step is performed withreference to additional information, said additional informationcomprising at least one of: product information; foundry information;process information; and layer information.
 9. The method as claimed inclaim 8, wherein said additional information is contained within tapeoutinformation.
 10. The method as claimed in claim 1, wherein said set ofpredetermined physical features is disposed in a predetermined layer ofsaid proprietary circuit layout.
 11. The method as claimed in claim 1,wherein said extracting step is performed with reference to apredetermined set of extraction rules.
 12. The method as claimed inclaim 1, wherein said extracting step comprises selecting a subset ofsaid predetermined physical features as said set of predeterminedphysical features.
 13. The method as claimed in claim 1, wherein saidlayout database file comprises at least one GDS-II file.
 14. The methodas claimed in claim 1, wherein said layout database file comprises atleast one of: an OASIS file; a GERBER file; and a DXF file.
 15. Themethod as claimed in claim 1, wherein said set of predetermined physicalfeatures comprises a set of contacts of said proprietary circuit layout.16. The method as claimed in claim 15, wherein said contacts aremetal-poly contacts.
 17. The method as claimed in claim 4, wherein saidfirst type of predetermined physical features comprises metal-polycontacts and said second type of predetermined physical featurescomprises diffusion contacts.
 18. The method as claimed in claim 1,wherein said set of predetermined physical features comprises featuresof said proprietary circuit layout selected from: features in adiffusion layer; features in a metal layer; vias; and/or transistorlocations and/or sizes.
 19. The method as claimed in claim 1, whereinsaid relative locations of said set of predetermined physical featuresof said proprietary circuit layout are defined by relative origins ofsaid set of predetermined physical features.
 20. The method as claimedin claim 1, wherein said set of predetermined physical featurescomprises circuitry components of said proprietary circuit layout.
 21. Amethod of identifying use of a proprietary circuit layout, the methodcomprising the steps of: inputting a representation of a layout of acircuit; identifying locations of a test set of predetermined physicalfeatures of said circuit from said representation; comparing saidlocations with a previously generated characteristic pattern file, saidcharacteristic pattern file comprising a representation of relativelocations of a characteristic set of predetermined physical features insaid proprietary circuit layout; and generating an output indicative ofa result of said comparing step.
 22. The method as claimed in claim 21,wherein said identifying step comprises: parsing said representation toidentify elements indicative of said test set of predetermined physicalfeatures; and determining said locations of said test set ofpredetermined physical features from said elements.
 23. The method asclaimed in claim 22, wherein said elements comprise geometric shapesrepresenting said test set of predetermined physical features.
 24. Themethod as claimed in claim 21, wherein said comparing step comprisespanning across said locations of said test set of predetermined physicalfeatures to seek a match with said characteristic set of predeterminedphysical features.
 25. The method as claimed in claim 22, wherein saidparsing step is performed with reference to additional informationcomprised in said representation, said additional information comprisingat least one of: product information; foundry information; processinformation; and layer information.
 26. The method as claimed in claim25, wherein said set of predetermined physical features is disposed in apredetermined layer of said circuit.
 27. The method as claimed in claim21, wherein said representation of said layout of said circuit comprisesa GDSII tapeout.
 28. The method as claimed in claim 21, wherein saidrepresentation of said layout of said circuit comprises at least one of:an OASIS file; a GERBER file; and a DXF file.
 29. The method as claimedin claim 21, wherein said test set of predetermined physical featurescomprises a set of contacts of said circuit.
 30. The method as claimedin claim 29, wherein said contacts are metal-poly contacts.
 31. Themethod as claimed in claim 21, wherein said test set of predeterminedphysical features comprises features of said circuit selected from:features in a diffusion layer; features in a metal layer; vias; and/ortransistor locations and/or sizes.
 32. The method as claimed in claim21, wherein said locations of said test set of predetermined physicalfeatures of said circuit are defined by relative origins of said set ofpredetermined physical features.
 33. The method as claimed in claim 21,wherein said test set of predetermined physical features comprisescircuitry components of said circuit.
 34. A data processing apparatusfor generating a characteristic pattern file to be used to identify useof a proprietary circuit layout, the data processing apparatuscomprising: input circuitry configured to input a layout database filecomprising a representation of said proprietary circuit layout;extraction circuitry configured to extract relative locations of a setof predetermined physical features of said proprietary circuit layoutfrom said layout database file; and generation circuitry configured togenerate said characteristic pattern file comprising a representation ofsaid relative locations of said set of predetermined physical featuresof said proprietary circuit layout.
 35. A data processing apparatus forgenerating a characteristic pattern file to be used to identify use of aproprietary circuit layout, the data processing apparatus comprising:input means for inputting a layout database file comprising arepresentation of said proprietary circuit layout; extraction means forextracting relative locations of a set of predetermined physicalfeatures of said proprietary circuit layout from said layout databasefile; and generation means for generating said characteristic patternfile comprising a representation of said relative locations of said setof predetermined physical features of said proprietary circuit layout.36. A computer-readable storage medium storing a computer program whichwhen executed causes a computer to carry out the method of claim
 1. 37.A data processing apparatus for identifying use of a proprietary circuitlayout, the data processing apparatus comprising: input circuitryconfigured to input a representation of a layout of a circuit;identification circuitry configured to identify locations of a test setof predetermined physical features of said circuit from saidrepresentation; comparison circuitry configured to compare saidlocations with a previously generated characteristic pattern file, saidcharacteristic pattern file comprising a representation of relativelocations of a characteristic set of predetermined physical features insaid proprietary circuit layout; and generation circuitry configured togenerate an output indicative of a result of said comparing step.
 38. Adata processing apparatus for identifying use of a proprietary circuitlayout, the data processing apparatus comprising: input means forinputting a representation of a layout of a circuit; identificationmeans for identifying locations of a test set of predetermined physicalfeatures of said circuit from said representation; comparison means forcomparing said locations with a previously generated characteristicpattern file, said characteristic pattern file comprising arepresentation of relative locations of a characteristic set ofpredetermined physical features in said proprietary circuit layout; andgeneration means for generating an output indicative of a result of saidcomparing step.
 39. A computer-readable storage medium storing acomputer program which when executed causes a computer to carry out themethod of claim 21.